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"%"+"6#!G#i####>#5$H$e$-}$B$$ %(%,;%h%>%%-%6 &>C&&&-&&7&!1'!S')u'-''*'-( .((9($b(2(('($()>4)%s)8))))*3*.L* {*-**'*.+.6+e+u+%+!+&+&+($,1M,(, ,, ,-+#-+O-{------+.!?.La.)..!.%/.?/6n/////0 ,0 M0n00C00.1<315p11%1J1'/2HW2>222'35736m303D3!43<41p434&4)4/'5W57k5-5951 6)=6"g6,666)6767FL7 777+787#8([88&8/8/8&9P:9&9499":/*:Z:,y:+:,:.:/.;"^;);";5;&<$+<P<4Y<<0</<#="&=9I=8=-=/=4><O>6>+>>7 ?2E?3x?*? ?#?H@5e@.@6@BADA[A%lAAA2AA B(B)HB1rB2B'B'B'C:;CvC#CCCCDD3/D+cD0D D<DE36EjEE.E$E.E&$FKF,kF(F(F+F G7G0JG%{GG G&G HH+H?H,\HHHH HHI-IAI/UI6I IGI$%J"JJmJJJJJJJKK-K"DKgKIK:KLL$8L]L{LLL L8L8MVMvMMMMMMNF8N/N,N'N5O8:OsO)OO(O:O":P(]P1PP(P!P$Q%T%cT%T%T$T%T% U%FU'lU#U$U$U%V#(V&LV"sV$V"V$V$W&(WOW'fW*W+W+W$X#6X#ZX!~X-X;X YN)YNxY=Y2Z#8Z+\Z+Z$Z=ZD[=\[4[[[0\2\ H\9i\4\7\R];c];]].]%%^HK^&^+^^O<0r _QV1w`Lb02`U& G*'Oo:Ph~[G3-?H \J-mq(p7gk Pk9.GzeFUjR<~i OlNGtyV\m&nvr={P=SbVH!h1/?V %y/+{XK_i*mv1Od2 .Q~7=6b(!3@#%t+teRZY' aeC;:P R&N&a(. o[g\,+c5N4 gr/;LoU _q6+hI,2:1;bIXo#C{"e:ZnA  8{49WCK#Mw( c"#!pWeUPaZ? ~K?<\$J<2vYY'(BLcbn]af7^i|~x ;iSQ%RBj, /S@|Jn%Jw7 gv;m h] 3? fu`RyaIOw|*UxLY VD<E@AJ`p+},S7dS"Pl+_w"sg[XSUFho$H`_  (WK {Ql\py}dDj _qJBx>R&"Z,&}c`MmWrudC' EPkzJ|M5x(A-e "|, #'n1$-YUE jBf@)Mqu|*amHj3 47>;>0}4^Y$);D8#*a|/d%T|3vrEw^o G@?`I^5MtZL5F9DA8^$mfCX{^UI[}XMWC5zvz  8Qc]O}!7tK6 !":q6(\T eWc[g B"D-.{4s*[pQ8h>h&]yp0&D6Vrrx3E=m6@g$#z{j./6H-Kq)>2?=j;fnsMy:/@aEdZ9[TrnZ`,+pQfI:+$H0T2C I9>-kzo=gx*]TXH'!1%_dGu=EwY5q%u >>)-ScsE !R/BxKR0kl.F?IFuO $i4G <, b4:x9 71]l _qs$'f9Tz^VGX~NL.)3N2MST) B} i%2NLctp^ktn9NTi5FWo'81FbfAbKuBP}iyYDV8J0)A'z~k%# <wsse3 !<h& *6v]HC8 t@= 04.N~)Z\!u][OAv\sdWjllyD"QLAk5XlF#  [default is %d] [default is %s] %s specify variant of 960 architecture -b add code to collect statistics about branches taken -link-relax preserve individual alignment directives so linker can do relaxing (b.out format only) -no-relax don't alter compare-and-branch instructions for long displacements specify variant of SPARC architecture -bump warn when assembler switches architectures -sparc ignored --enforce-aligned-data force .long, etc., to be aligned correctly -relax relax jumps and branches (default) -no-relax avoid changing any jumps and branches D30V options: -O Make adjacent short instructions parallel if possible. -n Warn about all NOPs inserted by the assembler. -N Warn about NOPs inserted after word multiplies. -c Warn about symbols whoes names match register names. -C Opposite of -C. -c is the default. Registers will not need any prefix. Registers will require a `$'-prefix. emulate output (default %s) Record the cpu type -V print assembler version number -Qy, -Qn ignored S390 options: -mregnames Allow symbolic names for registers -mwarn-areg-zero Warn about zero base/index registers -mno-regnames Do not allow symbolic names for registers -m31 Set file format to 31 bit format -m64 Set file format to 64 bit format --MD FILE write dependency information in FILE (default none) --defsym SYM=VAL define symbol SYM to given value --execstack require executable stack for this object --fatal-warnings treat warnings as errors --help show this message and exit --itbl INSTTBL extend instruction set to include instructions matching the specifications defined in file INSTTBL --listing-cont-lines set the maximum number of continuation lines used for the output data column of the listing --listing-lhs-width set the width in words of the output data column of the listing --listing-lhs-width2 set the width in words of the continuation lines of the output data column; ignored if smaller than the width of the first line --listing-rhs-width set the max width in characters of the lines from the source file --no-underscore User symbols do not have any prefix. --noexecstack don't require executable stack for this object --pic Enable generation of position-independent code. --statistics print various measured statistics from execution --strip-local-absolute strip local absolute symbols --target-help show target specific options --traditional-format Use same format as native assembler when possible --underscore User symbols are normally prepended with underscore. --version print assembler version number and exit --warn don't suppress warnings -D produce assembler debugging messages -EB assemble code for a big-endian cpu -EL assemble code for a little-endian cpu -I DIR add DIR to search list for .include directives -J don't warn about signed overflow -K warn when differences altered for long displacements -L,--keep-locals keep local symbols (e.g. starting with `L') -M,--mri assemble in MRI compatibility mode -N Warn when branches are expanded to jumps. -Q ignored -R fold data section into text section -V print assembler version number -Qy, -Qn ignored -W --no-warn suppress warnings -Wnp synonym for -no-warn-explicit-parallel-conflicts -Wnuh synonym for -no-warn-unmatched-high -Wp synonym for -warn-explicit-parallel-conflicts -Wuh synonym for -warn-unmatched-high -X ignored -Z generate object file even after errors -c print a warning if a comment is found -f skip whitespace and comment preprocessing -fixed-special-register-names Allow only the original special register names. -globalize-symbols Make all symbols global. -gnu-syntax Turn off mmixal syntax compatibility. -h, -H Don't execute, print this help text. Deprecated. -linker-allocated-gregs If there's no suitable GREG definition for the operands of an instruction, let the linker resolve. -m32r disable support for the m32rx instruction set -m32rx support the extended m32rx instruction set -mall-opcodes accept all AVR opcodes, even if not supported by MCU -mno-skip-bug disable warnings for skipping two-word instructions (default for avr4, avr5) -mno-wrap reject rjmp/rcall instructions with 8K wrap-around (default for avr3, avr5) -mip2022 restrict to IP2022 insns -mip2022ext permit extended IP2022 insn -mrelax Enable relaxation -mv850 The code is targeted at the v850 -mv850any The code is generic, despite any processor specific instructions -mv850e The code is targeted at the v850e -mwarn-signed-overflow Warn if signed immediate values overflow -mwarn-unsigned-overflow Warn if unsigned immediate values overflow -n Do not optimize code alignment -q quieten some warnings -no-expand Do not expand GETA, branches, PUSHJ or JUMP into multiple instructions. -no-merge-gregs Do not merge GREG definitions with nearby values. -no-predefined-syms Do not provide mmixal built-in constants. Implies -fixed-special-register-names. -no-warn-explicit-parallel-conflicts do not warn when parallel -no-warn-unmatched-high do not warn about missing low relocs -nocpp ignored -o OBJFILE name the object-file output OBJFILE (default a.out) -relax Create linker relaxable code. -w ignored -warn-explicit-parallel-conflicts warn when parallel instructions -warn-unmatched-high warn when an (s)high reloc has no matching low reloc -x Do not warn when an operand to GETA, a branch, PUSHJ or JUMP is not known to be within range. The linker will catch any errors. Implies -linker-allocated-gregs. (Requires %s; requested architecture is %s.) *input_line_pointer == '%c' 0x%02x ARM-specific assembler options: FR30 specific command line options: M32R specific command line options: MMIX-specific command line options: V850 options: XSTORMY16 specific command line options: Z8K options: -z8001 generate segmented code -z8002 generate unsegmented code -linkrelax create linker relaxable code !%s does not use a sequence number!samegp reloc against symbol without .prologue: %s"%d" (instance number %d of a %s label)".else" without matching ".if"".elseif" after ".else"".elseif" without matching ".if"".endif" without ".if"# Example of `%s' instructions .sect .text _start: # bars register# conflicts length#4 not valid on H8/300.###% operator needs absolute expression%d error%s, %d warning%s, generating bad object file%d error%s, %d warning%s, no object file generated%d warnings, treating warnings as errors%s -- statement `%s' ignored%s NOP inserted%s `%s' already has an alias `%s'%s register same as write-back base%s relocations do not fit in %d bytes%s relocations do not fit in %d bytes %s shortened to %s%s symbol recursion stopped at second appearance of '%s'%s unsupported%s without %s%s: data size %ld %s: global symbols not supported in common sections%s: no such section%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?%s: total time in assembly: %ld.%06ld %s: unexpected function type: %d%s: unrecognized processor name%s:%u: bad return from bfd_install_relocation: %x'%s' is not repeatable. Resulting behavior is undefined.'%s': only the NOP instruction can be issued in parallel on the m32r')' required'[' expected after PLD mnemonic'entry_num' must be absolute number in [0,31](PC)+ unpredictable(unknown reason)*-%s conflicts with the other architecture options, which imply -%s-(PC) unpredictable--gstabs is not supported for ia64--no-underscore is invalid with a.out format-32 create 32 bit object file -64 create 64 bit object file -32 create o32 ABI object file (default) -n32 create n32 ABI object file -64 create 64 ABI object file -32 is supported for ELF format only-64 is supported for ELF format only-EL generate code for a little endian machine -EB generate code for a big endian machine --little-endian-data generate code for a machine having big endian instructions and little endian data. -G may not be used with SVR4 PIC code-G n Data >= n bytes is in small data area -G not supported in this configuration.-KPIC generate PIC -V print assembler version number -undeclared-regs ignore application global register usage without appropriate .register directive (default) -no-undeclared-regs force error on application global register usage without appropriate .register directive -q ignored -Qy, -Qn ignored -s ignored -R option not supported on this target.-TSO use Total Store Ordering -PSO use Partial Store Ordering -RMO use Relaxed Memory Ordering -call_shared is supported only for ELF format-expand-pt32 invalid together with -no-expand-expand-pt32 only valid with -abi=64-k generate PIC -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated. -no-mCPU don't generate code specific to CPU. For -mCPU and -no-mCPU, CPU must be one of: -mPIC Note large position independent code -mabi is supported for ELF format only-mcpu= Specify the CPU version -mdouble Note fp double insns are used -mdword Note stack is aligned to a 8 byte boundary -me Redirect errors to a file -merrors-to-file -mfar-mode | -mf Use extended addressing -mfpr-32 Note 32 fprs are used -mfpr-64 Note 64 fprs are used -mgp32 used with a 64-bit ABI-mgp64 used with a 32-bit ABI-mgp64 used with a 32-bit processor-mgpr-32 Note 32 gprs are used -mgpr-64 Note 64 gprs are used -mips16 generate mips16 instructions -no-mips16 do not generate mips16 instructions -mlibrary-pic Compile library for large position indepedent code -mmedia Note media insns are used -mmuladd Note multiply add/subtract insns are used -mno-dword Note stack is aligned to a 4 byte boundary -mno-pack Do not allow instructions to be packed -mpack Note instructions are packed -mpic Note small position independent code -mrelocatable support for GCC's -mrelocatble option -mrelocatable-lib support for GCC's -mrelocatble-lib option -memb set PPC_EMB bit in ELF flags -mlittle, -mlittle-endian, -l, -le generate code for a little endian machine -mbig, -mbig-endian, -b, -be generate code for a big endian machine -msolaris generate code for Solaris -mno-solaris do not generate code for Solaris -V print assembler version number -Qy, -Qn ignored -msoft-float Note software fp is used -mtomcat-debug Debug tomcat workarounds -mtomcat-stats Print out stats for tomcat workarounds -n32 is supported for ELF format only-no-expand only valid with SHcompact or SHmedia-no-mix is invalid without specifying SHcompact or SHmedia-non_shared is supported only for ELF format-shcompact-const-crange is invalid without SHcompact....COMMon length (%d.) < 0! Ignored..COMMon length (%ld.) <0! Ignored..COMMon length (%lu) out of range ignored.EQU must use a label.EXIT must appear within a procedure.REG expression must be a register.REG must use a label.SCOMMon length (%ld.) <0! Ignored..abort detected. Abandoning ship..begin directive with no matching .end directive.begin directive without a preceding .ent directive.begin directive without a preceding .file directive.begin/.bend in different segments.bend directive names unknown symbol.bend directive without a preceding .ent directive.bend directive without a preceding .file directive.callinfo is not within a procedure definition.cfi_endproc without corresponding .cfi_startproc.cpload not in noreorder section.def pseudo-op used inside of .def/.endef: ignored..def pseudo-op used inside of .def/.endef; ignored.dim pseudo-op used outside of .def/.endef: ignored..dim pseudo-op used outside of .def/.endef; ignored.ef with no preceding .function.end directive has no name.end directive missing or unknown symbol.end directive names different symbol than .ent.end directive names unknown symbol.end directive without a preceding .ent directive.end directive without a preceding .ent directive..end directive without a preceding .file directive.end directive without matching .ent.end not in text section.end symbol does not match .ent symbol..end%s without preceding .%s.endef pseudo-op used before .def; ignored.endef pseudo-op used outside of .def/.endef: ignored..endfunc missing for previous .func.endfunc missing for previous .proc.ent directive has no name.ent directive has no symbol.ent directive without matching .end.ent or .aent not in text section..err encountered.es without preceding .bs.fail %ld encountered.field count '%d' out of range (1 <= X <= 32).fill size clamped to %d.fmask outside of .ent.frame outside of .ent.ifeqs syntax error.incbin count zero, ignoring `%s'.linkonce is not supported for this object file format.literal_position inside literal directive; ignoring.ln pseudo-op inside .def/.endef: ignored..loc before .file.loc outside of .text.loc pseudo-op inside .def/.endef: ignored..mask outside of .ent.mask/.fmask outside of .ent.name directive has no symbol.name directive not in link (.link) section.option pic%d not supported.pdesc directive has no entry symbol.pdesc directive not in link (.link) section.pdesc has no matching .ent.popsection without corresponding .pushsection; ignored.previous without corresponding .section; ignored.prologue directive without a preceding .ent directive.sblock may be used for initialized sections only.scl pseudo-op used outside of .def/.endef ignored..scl pseudo-op used outside of .def/.endef; ignored.set pop with no .set push.size expression too complicated to fix up.size pseudo-op used outside of .def/.endef ignored..size pseudo-op used outside of .def/.endef; ignored.space or .fill with negative value, ignored.space repeat count is negative, ignored.space repeat count is zero, ignored.space specifies non-absolute value.space/.bes repeat count is negative, ignored.space/.bes repeat count is zero, ignored.stab%c is not supported.stab%c: description field '%x' too big, try a different debug format.stab%c: ignoring non-zero other field.stab%c: missing comma.syntax %s requires command-line option `--no-underscore'.syntax %s requires command-line option `--underscore'.tag pseudo-op used outside of .def/.endef ignored..tag pseudo-op used outside of .def/.endef; ignored.tag requires a structure tag.tag target '%s' undefined.tc not in .toc section.tc with no label.type pseudo-op used outside of .def/.endef ignored..type pseudo-op used outside of .def/.endef; ignored.usepv directive has no name.usepv directive has no type.uses does not refer to a local symbol in the same section.uses pseudo-op seen when not relaxing.uses target does not refer to a local symbol in the same section.val pseudo-op used outside of .def/.endef ignored..val pseudo-op used outside of .def/.endef; ignored.var may only be used within a macro definition.word %s-%s+%s didn't fit0x%lx: "%s" type = %ld, class = %d, segment = %d 16-bit jump out of range32-bit conditional branch generated32bit mode not supported on this CPU.5-bit field must be absolute5-bit immediate too large62-bit relocation not yet implemented64bit mode not supported on this CPU.68000 or higher68010 or higher68020 or higher68040 and 68851 specified; mmu instructions may assemble incorrectly: PC-relative operand can't be a constant: TLS operand can't be a constant: There are only 32 f registers; [0-31]: There are only 64 f registers; [0-63]: asr number must be between 0 and 31: asr number must be between 16 and 31: expecting %asrN: invalid ASI expression: invalid ASI name: invalid ASI number: invalid cpreg name: invalid membar mask expression: invalid membar mask name: invalid membar mask number: invalid prefetch function expression: invalid prefetch function name: invalid prefetch function number: invalid siam mode expression: invalid siam mode number: rd on write only ancillary state register: unrecognizable privileged register: unrecognizable v9a ancillary state register: unrecognizable v9a or v9b ancillary state register:b not permitted; defaulting to :w assemble for architecture assemble for CPU assemble for FPU architecture ,X